PCIe3: Root Complex, no link, regs 0xfe202000įman1: Uploading microcode version 101.8.0 ![]() PCIe1: Root Complex, no link, regs 0xfe200000 Warning: SERDES bank 3 expects reference clock 100MHz, but actual is 125MHzįman1: Data at ef000000 is not a firmware Warning: SERDES bank 2 expects reference clock 100MHz, but actual is 125MHz *** Warning - bad CRC, using default environment ![]() SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125MhzĭDR Chip-Select Interleaving Mode: CS0+CS1
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